Advance in semiconductor technology enables the dimensions of semiconductor devices to decrease. As the dimensions of semiconductor devices decrease, contact resistances of a MOS transistor are having increasing impact on the performance of the MOS transistor and/or even the entire semiconductor chip. To improve the performance of semiconductor chips, contact resistances of a MOS transistor need to be reduced. Among the contact resistances in a MOS transistor, the contact resistance between the source/drain and the corresponding conductive plug can be undesirably high due to the relatively small areas of the source and the drain regions. Thus, the relatively high contact resistance may cause the performance of the MOS transistor to be adversely affected and significantly slow down the operating speed of the semiconductor device/chip.
Silicide layer (metal-semiconductor (silicon) compound) formed on the surfaces of the source and drain regions through a salicide (self-aligned silicide layer) process can effectively reduce the contact resistance between the source/drain and the corresponding conductive plug. In existing semiconductor technologies, the self-aligned silicide layer is often formed by evaporating or sputtering a metal layer on poly-silicon. A thermal annealing process is often performed after the evaporation/sputtering process to enable the formation of silicide layer through the reaction between the metal and the substrate material (i.e., the poly-silicon). Then, unreacted metal layer is removed.
As the dimensions of the semiconductor devices further continue to decrease, the contact resistances of transistors are having more prominent impact on the performance of the semiconductor devices. Since the contact resistances between the source and drain regions and the corresponding silicide layers account for a main portion of the total contact resistances of a transistor, the contact resistance between the source/drain and the corresponding silicide layer needs to be further reduced to reduce the contact resistances of the transistor.